Viterbi Decoder and Method Thereof

ABSTRACT

The present invention relates to a decoder for tail-biting convolution codes and a method thereof. The decoder receives an encoding bit sequence in a convolutional encoding method from a channel, generates an expanded encoding bit sequence, Viterbi decodes the expanded encoding bit sequence, and generates decoded data. In addition, the decoder selects a central bit sequence of the decoded data, rearranges the central bit sequence, and generates final decoded data. Accordingly, the decoder has a simplified configuration for decoding the bit sequence encoded in the tail biting convolutional encoding method, and the decoder also decodes a bit sequence encoded in a zero-tail convolutional encoding method.

TECHNICAL FIELD

The present invention relates to a Viterbi decoder and a method thereof,and more specifically, to a decoder for tail-biting convolution codesand a method thereof.

BACKGROUND ART

Various digital communication standards have adopted a convolutionalcoding method for a forward error correction (FCE).

An information bit sequence encoded in the convolutional coding methodis decoded by a Viterbi decoder in a receiver.

FIG. 1 shows a diagram of a configuration of a convolutional encoderhaving a constraint length K of 7 according to the internationalstandard IEEE 802.16.

As shown in FIG. 1, the convolutional encoder having the constraintlength K of 7 according the international standard IEEE 802.16 includestwo XOR operators 11 and 12 and six delay units 21 to 26. Theconvolutional encoder receives one bit among the information bitsequence for every clock signal through a first delay unit 21, andgenerates two encoded symbols by the two XOR operators 11 and 12. Theconvolutional code is classified as a zero-tail convolutional code and atail-biting convolutional code.

The zero-tail convolutional encoding method will now be described withreference to FIG. 2 to FIG. 4.

FIG. 2 shows a diagram for representing an encoding unit packet of anencoder in the zero-tail convolutional encoding method.

As shown in FIG. 2, the encoding unit packet of the encoder in thezero-tail convolutional encoding method is formed by adding a sequenceof (K-1) zero-bits (a zero-tail sequence) to the information bitsequence. Therefore, when the number of the information bits is L, thenumber of bits of the encoding unit packet of the encoder in thezero-tail convolutional encoding method is L+K-1. Since the constraintlength K is 7 in an exemplary embodiment of the present invention, theencoding unit packet includes L+6 bits.

FIG. 3 shows a diagram for representing an initial state of the encoderin the zero-tail convolutional encoding method. As shown in FIG. 3, eachdelay unit has a value of 0 when the encoder in the zero-tailconvolutional encoding method is at the initial state. Therefore, aViterbi decoder in the zero-tail convolutional encoding method may starta decoding operation from the 0 state.

FIG. 4 shows a diagram for representing an ending state of the encoderin the zero-tail convolutional encoding method. As shown in FIG. 4, theending state of the encoder in the zero-tail convolutional encodingmethod is the 0 state in which each delay unit has the value of 0. Since0 values of the last K-1 bits of the encoding unit packet are inputtedto the convolutional encoder, the ending state of the encoder in thezero-tail convolutional encoding method is becomes the 0 state.Therefore, the Viterbi decoder in the zero-tail convolutional encodingmethod may start a trace back operation from the 0 state.

Since the additional zero tail sequence having the values of 0 is usedin the zero-tail convolutional encoding method, an error may be easilycorrected when a last part of the information bit sequence has theerror. In addition, the Viterbi decoder may start the decoding and traceback operations from the 0 state since both the initial and endingstates of the convolutional encoder are 0, and therefore a configurationof the Viterbi decoder may be simplified. However, there is a problem inthat the data rate is reduced due to the additional zero tail sequencein the zero-tail convolutional encoding method. To solve the problem,the tail biting convolutional encoding method has been suggested.

The tail biting convolutional encoding method will now be described withreference to FIG. 5 to FIG. 7.

FIG. 5 shows a diagram for representing an encoding unit packet of anencoder in the tail biting convolutional encoding method. As shown inFIG. 5, the encoding unit packet of the encoder in the tail bitingconvolutional encoding method has no additional data. Therefore, thedata rate in the tail biting convolutional encoding method is betterthan that in the zero-tail convolutional encoding method.

FIG. 6 shows a diagram for representing an initial state of the encoderin the tail biting convolutional encoding method. As shown in FIG. 6,the initial state of the encoder in the tail biting convolutionalencoding method is determined by the last 6 bits of the encoding unitpacket. Since the last 6 bits of the encoding unit packet of the encoderin the tail biting convolutional encoding method are respectively not 0,the initial state of the encoder in the tail biting convolutionalencoding method is not 0.

The encoder in the tail biting convolutional encoding methodpreferentially receives the last 6 bits of the encoding unit packetbefore performing an encoding operation, so as to establish the initialstate of the encoder as the last 6 bits of the decoding unit packet. Atthis time, the encoder in the tail biting convolutional encoding methoddoes not generate an encoded output bit. Then, the encoder in the tailbiting convolutional encoding method sequentially receives theinformation bit sequence, and generates the encoded output bit.

FIG. 7 shows a diagram for representing the ending state of the encoderin the tail biting convolutional encoding method. As shown in FIG. 7,differing from the zero-tail convolutional encoding method, the endingstate in the tail biting convolutional encoding method is determined bythe last 6 bits of the information bit sequence since the ending stateincludes no additional zero-bit. Therefore, the initial and endingstates of the encoder in the tail biting convolutional encoding methodare the same.

In addition, the initial and ending states of the encoder in the tailbiting convolutional encoding method are not 0 since those aredetermined by the last 6 bits of the encoding unit packet. Therefore,the Viterbi decoder in the tail biting convolutional encoding method hasa problem of determining the initial state for the decoding and traceback back operations, and therefore the configuration of the Viterbidecoder is problematically complicated. In addition, the initial statefor the trace back operation may be falsely determined and the finaldecoded information bit sequence may include an error when the last partof the encoding unit packet has errors.

The above information disclosed in this Background section is only forenhancement of understanding of the background of the invention andtherefore it may contain information that does not form the prior artthat is already known in this country to a person of ordinary skill inthe art.

DISCLOSURE OF INVENTION Technical Problem

The present invention has been made in an effort to provide a simplifiedViterbi decoder of a tail biting convolutional encoding scheme and amethod thereof.

Technical Solution

An exemplary Viterbi decoder according to an embodiment of the presentinvention includes a receiving buffer, a received bit sequence expandingunit, a Viterbi decoding unit, a central bit sequence selector, and arearrange unit. The receiving buffer receives an encoding bit sequencein a convolutional encoding method from a channel. The received bitsequence expanding unit receives the encoding bit sequence correspondingto an encoding unit from the receiving buffer, and generates an expandedencoding bit sequence by expanding the encoding bit sequence more thantwice (some of the initial bit sequence or the last bit sequence of theexpanded encoding bit sequence may be omitted). The Viterbi decodingunit receives the expanded encoding bit sequence, Viterbi decodes theexpanded bit sequence, and outputs decoded data. The central bitsequence selector selects a central bit sequence of the decoded data,and outputs the central bit sequence. The rearrange unit rearranges anorder of the central bit sequence, and generates final decoded data.

The Viterbi decoding unit may include a branch metric calculator, an ACSoperator, and a trace back unit. The branch metric calculator calculatesbranch metrics of branches by differences between the expanded encodingbit sequence and encodes bits on a trellis of a transmitterconvolutional encoder. The ACS operator adds the branch metrics toprevious state path metrics, calculates metrics of paths from therespective branches to a current state, and selects a survival path fora path having a minimum path metric. The trace back unit traces back thesurvival path, and outputs decoded data.

In addition, the ACS operator may include a path metric adder, a pathmetric comparator, a path metric selector, and a path metric storageunit. The path metric adder adds the previous state path metrics tobranch metrics of branches from the previous state to the current state,and generates the metrics of paths from the respective branches to thecurrent state. The path metric comparator compares the metrics of pathsgenerated by the path metric adder, and selects the survival path havingthe minimum path metric. The path metric selector selects a path metriccorresponding to the survival path and outputs the selected path metric.The path metric storage unit stores the selected path metric.

In an exemplary decoding method according to another embodiment of thepresent invention, a) an encoding bit sequence in a convolutionalencoding method is received from a channel, b) an expanded encoding bitsequence for an encoding unit based on the encoding bit sequence (theexpanded encoding bit sequence is generated by expanding the encodingbit sequence more than twice, and some of the initial bit sequence andthe last bit sequence of the expanded encoding bit sequence may beomitted) is generated, c) the expanded encoding bit sequence is Viterbidecoded and decoded data are outputted, d) a central bit sequence of thedecoded data is selected, and e) an order of the central bit sequence isrearranged and final decoded data are generated.

Advantageous Effects

According to the exemplary embodiment of the present invention, a bitsequence encoded in the tail biting convolutional encoding method may bedecoded by a simple decoding device.

In addition, according to the exemplary embodiment of the presentinvention, bit sequences respectively encoded in the tail bitingconvolutional encoding method and the zero-tail convolutional encodingmethod may be decoded by one decoding device.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 shows a diagram of a configuration of a convolutional encoderhaving a constraint length K of 7 according an international standardIEEE 802.16.

FIG. 2 shows a diagram for representing an encoding unit packet of anencoder in a zero-tail convolutional encoding method.

FIG. 3 shows a diagram for representing an initial state of the encoderin the zero-tail convolutional encoding method.

FIG. 4 shows a diagram for representing an ending state of the encoderin the zero-tail convolutional encoding method.

FIG. 5 shows a diagram for representing an encoding unit packet of anencoder in a tail biting convolutional encoding method.

FIG. 6 shows a diagram for representing an initial state of the encoderin the tail biting convolutional encoding method.

FIG. 7 shows a diagram for representing the ending state of the encoderin the tail biting convolutional encoding method.

FIG. 8 shows a diagram of a configuration of a Viterbi decoder accordingto a first exemplary embodiment of the present invention.

FIG. 9 shows a diagram for representing the Viterbi decoder according toa second exemplary embodiment of the present invention.

FIG. 10 shows a diagram for representing the Viterbi decoder accordingto a third exemplary embodiment of the present invention.

FIG. 11 shows a diagram for representing the Viterbi decoder accordingto a fourth exemplary embodiment of the present invention.

FIG. 12 shows a diagram for representing the Viterbi decoder accordingto a fifth exemplary embodiment of the present invention.

FIG. 13 shows a block diagram for representing a Viterbi decoding unitaccording to the exemplary embodiment of the present invention.

FIG. 14 shows a diagram for representing a branch metric calculatoraccording to the exemplary embodiment of the present invention.

FIG. 15 shows a diagram for representing an ACS operator according tothe exemplary embodiment of the present invention.

FIG. 16 shows a normalizing factor generator 329 according to theexemplary embodiment of the present invention.

FIG. 17 shows a diagram for representing a trace back unit according tothe exemplary embodiment of the present invention.

FIG. 18 shows a flowchart for representing the decoding method accordingto the exemplary embodiment of the present invention.

FIG. 19 shows a flowchart for representing the Viterbi decoding methodaccording to the exemplary embodiment of the present invention.

FIG. 20 shows a flowchart for representing steps for generating thebranch metrics and ACS operation steps according to the exemplaryembodiment of the present invention.

BEST MODE FOR CARRYING OUT THE INVENTION

An exemplary embodiment of the present invention will hereinafter bedescribed in detail with reference to the accompanying drawings.

In the following detailed description, only certain exemplaryembodiments of the present invention have been shown and described,simply by way of illustration. As those skilled in the art wouldrealize, the described embodiments may be modified in various differentways, all without departing from the spirit or scope of the presentinvention. In addition, the drawings and description are to be regardedas illustrative in nature and not restrictive, and like referencenumerals designate like elements throughout the specification.

Throughout this specification and the claims which follow, unlessexplicitly described to the contrary, the word “comprise” or variationssuch as “comprises” or “comprising” will be understood to imply theinclusion of stated elements but not the exclusion of any otherelements.

While a transmitter uses a convolution encoder having a constraintlength K of 7 according to the IEEE802.16 international standard in anexemplary embodiment of the present invention, it is to be understoodthat the present invention covers various convolutional encoders.

In the exemplary embodiment of the present invention, the convolutionalencoder uses a tail biting convolutional encoding method.

In addition, L denotes an encoding unit size of the convolutionalencoder. At this time, when a code rate of the convolutional encoder isk/n, an encoded output bit sequence of the convolutional encoder will beL*n/k (hereinafter, L*n/k will also be referred to as M). When theconstraint length of the convolutional encoder is 7 according to theIEEE802.16, the encoded output bit sequence of the convolutional encoderwill be 2L. Hereinafter, a length of the encoded output bit sequencewill be referred to as L*n/k in the exemplary embodiment of the presentinvention.

A Viterbi decoder according to the exemplary embodiment of the presentinvention will now be described with reference to FIG. 8 to FIG. 12.

FIG. 8 shows a diagram of a configuration of the Viterbi decoderaccording to a first exemplary embodiment of the present invention.

As shown in FIG. 8, the Viterbi decoder according to the exemplaryembodiment of the present invention includes a receiving buffer 100, areceived bit sequence expanding unit 200, a Viterbi decoding unit 300, acentral bit sequence selector 400, a rearrange unit 500, and an outputbuffer 600.

The receiving buffer 100 receives an encoding bit sequence of the tailbiting convolutional encoding method through a channel.

The received bit sequence expanding unit 200 receives a sequence ofL*n/k encoding bits corresponding to the encoding unit L of theconvolutional encoder from the receiving buffer 100. In addition, thereceived bit sequence expanding unit 200 generates an expanded encodingbit sequence based on the received encoding bit sequence. As shown inFIG. 8, the expanded encoding bit sequence according to the firstexemplary embodiment of the present invention is a signal generated byoutputting the encoding bit sequence twice.

The Viterbi decoding unit 300 decodes the expanded encoding bit sequenceaccording to the Viterbi decoding method. The Viterbi decoding unit 300outputs 2L expanded decoded data since the Viterbi decoding unit 300receives the sequence of 2*L*n/k encoding bits. In addition, the Viterbidecoding unit 300 may use various Viterbi decoding methods including aRadix-2 method and a Radix-4 method.

The central bit sequence selector 400 selects a sequence of L centralbits d

L/2+1] , . . . , d[L], d[1], . . . , and d[L/2] among the 2L expandeddecoded datadecoded generated by the Viterbi decoding unit 300, andoutputs the selected sequence. While the central bit sequence selector400 selects the sequence of the exactly central bits to output theselected sequence in the exemplary embodiment of the present invention,it may select a bit sequence that is moved from the center a little aserrors may not occur. An operation of the Viterbi decoding unit 300 isdivided as a decoding operation and a trace back operation, and initialstates of the decoding and trace back operations may not be easilyobtained in the tail biting convolutional encoding method. It is quiteprobable that the initial L/2 bits d[1], . . . , and d[L/2] of thedecoded datadecoded may have an error since the initial state of thedecoding operation differs from the initial state of the convolutionalencoder according to characteristics of the tail biting convolutionalencoding method, when an Viterbi operation according to the exemplaryembodiment of the present invention is performed. Therefore, the centralbit sequence selector 400 does not output the initial L/2 bits of thedecoded datadecoded. It is also probable that the last L/2 bitsd[L/2+1], . . . , d[L]) of the decoded datadecoded may have an errorsince the initial state of the trace back operation differs from theending state of the convolutional encoder according to characteristicsof the tail biting convolutional encoding method, when the decodingoperation according to the exemplary embodiment of the present inventionis performed. Therefore, the central bit sequence selector 400 does notoutput the L/2 last bits of the decoded datadecoded.

The rearrange unit 500 rearranges the sequence of the central bitsselected by the central bit sequence selector 400 and outputs finaldecoded datadecoded. That is, the rearrange unit 500 outputs a sequenceof former half bits d[L/2+1], . . . , and d[L] of the central bitsequence after outputting a sequence of the latter half bits d[L/2+1], .. . , and d[L] thereof. Accordingly, the sequence of latter half bitsd[L/2+1], . . . , and d[L] of the central bit sequence is to be asequence of former half bits d[1], . . . , and d[L/2] of the finaldecoded datadecoded.

The output buffer 600 stores the final decoded datadecoded and outputthe stored final decoded datadecoded in 8 bits or 16 bits according tothe conditions.

FIG. 9 shows a diagram for representing the Viterbi decoder according toa second exemplary embodiment of the present invention.

As shown in FIG. 9, the received bit sequence expanding unit 200 of theViterbi decoder according to the second exemplary embodiment of thepresent invention generates the expanded encoding bit sequence byoutputting the received encoding bit sequence three times.

The Viterbi decoding unit 300 receiving the three-times expandedencoding bit sequence generates expanded decoded datadecoded which isthree times longer than the length L of the original information bit.

At this time, since it is quit probable that the expanded former halfand latter half bit sequences of the expanded decoded datadecoded mayhave an error due to the decoding and trace back operations at anarbitrary state, the central bit sequence selector 400 selects asequence of central bits of the expanded decoded datadecoded and outputsthe selected sequence.

As shown in FIG. 9, since the central bit sequence selector 400according to the second exemplary embodiment of the present inventionselects the sequence of the exactly central bits, the rearrange unit 500may bypass the received central bit sequence.

FIG. 10 shows a diagram for representing the Viterbi decoder accordingto a third exemplary embodiment of the present invention.

As shown in FIG. 10, the received bit sequence expanding unit 200 of theViterbi decoder according to the third exemplary embodiment of thepresent invention may generate the expanded encoding bit sequence byoutputting the received encoding bit sequence four times. That is, thereceived bit sequence expanding unit 200 generates the expanded encodingbit sequence by outputting the received encoding bit sequence more thantwo times. As the information bit sequence is expanded, the decodingperformance may be effectively increased when the length L of theinformation bit sequence is short.

FIG. 11 shows a diagram for representing the Viterbi decoder accordingto a fourth exemplary embodiment of the present invention.

As shown in FIG. 11, an initial bit of the expanded encoding bitsequence generated by the received bit sequence expanding unit 200 isnot necessarily the initial bit of the received encoding bit sequence,and a last bit of the expanded encoding bit sequence is not necessarilythe last bit of the encoding bit sequence.

As shown in FIG. 11, the received bit sequence expanding unit 200according to the fourth exemplary embodiment of the present inventiongenerates the expanded encoding bit sequence by outputting the receivedencoding bit sequence three times, and does not output a sequence offirst p bits and a sequence of last q bits.

FIG. 12 shows a diagram for representing the Viterbi decoder accordingto a fifth exemplary embodiment of the present invention.

In the fifth exemplary embodiment of the present invention, the centralbit sequence selector 400 is not required to select the sequence of theexact central bits of the expanded encoding data.

As shown in FIG. 12, the Viterbi decoder according to the fifthexemplary embodiment of the present invention selects a bit sequenceshifted from the center of the expanded decoded datadecoded to the leftby i bits and outputs the selected bit sequence. At this time, therearrange unit 500 generates the final decoded datadecoded according tothe moved central bit sequence.

The Viterbi decoding unit 300 will now be described with reference toFIG. 13.

FIG. 13 shows a block diagram for representing the Viterbi decoding unit300 according to the exemplary embodiment of the present invention.

As shown in FIG. 13, the Viterbi decoding unit 300 according to theexemplary embodiment of the present invention includes a branch metriccalculator 310, an ACS operator 320, and a trace back unit 330.

The branch metric calculator 310 calculates branch metrics on respectivebranches by differences between the expanded encoding bit sequencereceived from the received bit sequence expanding unit 200 and encodingbits on a trellis of a transmitter convolutional encoder (the encodingbits on the trellis are also referred to as branch coded word (BCW)).

The ACS operator 320 adds a previous path metric to the branch metriccalculated by the branch metric calculator 310 to calculate metrics ofpaths from the respective branches to a current state. In addition, theACS operator 320 compares the metrics of paths from the respectivebranches to find a minimum path metric, and selects a survival pathhaving the minimum path metric.

The trace back unit 330 traces back the trellis of the transmitterconvolutional encoder based on the survival path from the ACS operator320, and generates the expanded encoding data.

The branch metric calculator 310 will now be described with reference toFIG. 14.

FIG. 14 shows a diagram for representing the branch metric calculator310 according to the exemplary embodiment of the present invention.

The Viterbi decoding unit 300 according to the exemplary embodiment ofthe present invention has a Radix-2 configuration and uses 4-bit softdecision binary data. The Radix-2 Viterbi decoder generates four branchmetrics.

As shown in FIG. 14, the branch metric calculator 310 according to theexemplary embodiment of the present invention includes a distancecalculator 311, a branch metric adder 312, and a branch metric storageunit 313.

The distance calculator 311 calculates a distance value between an inputvalue of the Viterbi decoding unit 300 and representative values of 0and 1. The representative values of 0 and 1 are respectively 7 and 8.

The branch metric adder 312 generates the branch metrics according to astate transition by the distance values generated by the distancecalculator 311. Since the Viterbi decoding unit 300 according to theexemplary embodiment of the present invention has the Radix-2configuration, the branch metric adder 312 generates four branch metricsBM_(—)00, BM_(—)01, BM_(—)10, and BM_(—)11. The respective branchmetrics may be presented as 5 bits since they are obtained by adding two4-bit distance values calculated by the distance calculator 311.

The branch metric storage unit 313 stores the four branch metricsgenerated by the branch metric adder 312. Then, the branch metricsstored in the branch metric storage unit 313 are used to calculate thepath metric.

The ACS operator 320 will now be described with reference to FIG. 15 andFIG. 16.

FIG. 15 shows a diagram for representing the ACS operator 320 accordingto the exemplary embodiment of the present invention. FIG. 16 shows anormalizing factor generator 329 according to the exemplary embodimentof the present invention.

Since the transmitter according to the exemplary embodiment of thepresent invention uses the convolutional encoder having the constraintlength K of 7, the convolutional encoder has 64 states. Therefore, theACS operator 320 generates 64 path metrics and survival paths by 64operation blocks (the 64 operation blocks are shown without referencenumerals).

As shown in FIG. 15, the respective blocks of the ACS operator 320include two normalizing units 321 and 323, two path metric adders 322and 324, a path metric comparator 325, a path metric selector 326, apath metric clipper 327, and a path metric storage unit 328.

In addition, as shown in FIG. 16, the ACS operator 320 further includesa normalizing factor generator 329.

The normalizing factor generator 329 finds a normalizing factor (norm),a minimum path metric among the previous state path metrics, by aplurality of minimum path metric extractors 329 a.

The minimum value extractor 329 a according to the exemplary embodimentof the present invention receives the two previous path metrics andoutput the smaller value of the two. The minimum value extractor 329 aaccording to the exemplary embodiment of the present invention includesa comparator 329 a 1 and a selector 329 a 2. The comparator 329 a 1receives the two previous state path metrics, performs subtraction ofthe two values, and outputs an MSB among a result value of thesubtraction. When PM0 and PM1 denote the two previous state path metricsand R0 (=PM0-PM1) denotes the resulting value of the comparator 329 a 1,PM0>PM1 when the MSB of R0 is 0, and PM0<PM1 when the MSB R0 is 1. Theselector 329 a 2 is realized by a 5-bit 2-input multiplexer, and itselects an output value with reference to 1 bit information generated bythe comparator 329 a 1. Accordingly, the minimum value extractor 329 aaccording to the exemplary embodiment of the present invention selects aless value between PM0 and PM1, and outputs the minimum value.

In addition, the normalizing factor generator 329 binds the previousstate path metrics in pairs, and compares the respective pairs to findsmaller values of the pairs. Then, the normalizing factor generator 329binds the found smaller values in pairs, and compares the respectivepairs to find smaller values of the pairs. Accordingly, the normalizingfactor generator 329 finds the norm which is the minimum path metric.The found normalizing factor (norm) is stored in a normalizing factorstorage unit 329 b.

The operation blocks of the ACS operator 320 receive two path metrics(e.g., PM[0] and PM]1] in FIG. 15) of the previous states (e.g., 0 and 1states in FIG. 15), and finally selects the minimum path metric amongthe metrics of paths to the current state. In addition, the respectiveblocks of the ACS operator 320 generate a survival path (e.g., Tb[0] inFIG. 15) having the minimum path metric.

The two normalizing units 321 and 323 subtract the normalizing factor(norm) by the normalizing factor generator 329 from the two path metricsPM[0] and PM[1]. Accordingly, the path metric may be maintained at apredetermined number of bits (6 bits in the exemplary embodiment of thepresent invention) as the trellis of the transmitter convolutionalencoder proceeds.

The two path metric adders 322 and 324 add branch metrics (e.g.,BM_(—)00 and BM_(—)11) of branches, i.e., the branches from the previousstate to the current state, to the previous state path metrics PM[0] andPM[1], and generate the metrics of paths from the respective branches tothe current state.

The path metric comparator 325 receives the path metrics generated bythe path metric adders 322 and 324, performs subtraction of the pathmetrics, and outputs a 1-bit most significant bit (MSB) thereof. The1-bit outputted by the path metric comparator 325 is informationindicating the result of comparison between the two metrics of pathsfrom the respective branches to the current state, and is informationindicating the survival path. The 1-bit outputted by the path metriccomparator 325 as the survival path is stored in a survival path storageunit 331 in FIG. 17 of a trace back unit 330, as shown in FIG. 17. Thesurvival path storage unit 331 and the trace back unit 330 will bedescribed later.

The path metric selector 325 receives the 1-bit outputted by the pathmetric comparator 325, selects a smaller value among the metrics ofpaths from the respective branches to the current state, and outputs theselected value.

To maintain the selected value to be in 6 bits, the path metric clipper327 clips the selected value to be 111111₂ when the inputted value isequal to or greater than 1000000₂, and outputs the clipped value.Accordingly, the selected value may be maintained in 6 bits.

The metric of the path selected by the path metric selector 325, andclipped and outputted by the path metric clipper 327, is stored in thepath metric storage unit 328 to be used for generating a subsequentstate path metric.

The trace back unit 330 will now be described with reference to FIG. 17.

FIG. 17 shows a diagram for representing the trace back unit 330according to the exemplary embodiment of the present invention.

As shown in FIG. 17, the trace back unit 330 according to the exemplaryembodiment of the present invention includes a survival path storageunit 331, a down counter 332, a multimplexer 333, and a shift register334.

The survival paths generated by the path metric comparator 325 of therespective operation blocks of the ACS operator 320 are stored in thesurvival path storage unit 331. Since the number of the respectiveoperation blocks of the ACS operator 320 is 64, the survival path is64-bit information.

The down counter 332 reduces a memory address of the survival pathstorage unit 331 by 1 for each clock signal. Accordingly, the survivalpath storage unit 331 outputs a 64-bit survival path for each clocksignal.

The multiplexer 333 outputs 1 bit corresponding to 6 bits indicated bythe shift register 334. The shift register 334 inputs the received 1-bitto a least significant bit (LSB), and transmits a carry generated byshifting the 6-bit register to the central bit sequence selector 400. Aset of generated carries becomes the expanded decoded datadecoded.

The Viterbi decoding method according to the exemplary embodiment of thepresent invention will now be described with reference to FIG. 18 toFIG. 20.

FIG. 18 shows a flowchart for representing the decoding method accordingto the exemplary embodiment of the present invention, and FIG. 19 showsa flowchart for representing the Viterbi decoding method according tothe exemplary embodiment of the present invention. In addition, FIG. 20shows a flowchart for representing steps for generating the branchmetrics and ACS operation steps according to the exemplary embodiment ofthe present invention.

The receiving buffer 100 receives the encoding bit sequence from achannel in step S100.

The received bit sequence expanding unit 200 receives the encoding bitsequence corresponding to an encoding unit from the receiving buffer100, and outputs the expanded encoding bit sequence in step S200.

The Viterbi decoding unit 300 receives the expanded encoding bitsequence and Viterbi decodes the received bit sequence in step S300. TheViterbi decoding step S300 includes a branch metric calculating stepS310, an ACS operation step S320, and trace back step S330.

In the branch metric calculating step S310, the branch metrics for therespective branches are calculated by using differences between theexpanded encoding bit sequence received from the received bit sequenceexpanding unit 200 and the encoding bits (branch coded word, BCW) on thetrellis of the transmitter convolutional encoder. In further detail, thedistance calculator 311 calculates the distance value between the inputvalue of the Viterbi decoding unit 300 and the representative values of0 and 1 in step S311. The branch metric adder 312 generates the branchmetrics generated in the state transition by the distance valuegenerated by the distance calculator 311 in step S312.

In the ACS operation step S320, the metrics of paths from the respectivebranches to the current state are calculated by adding the branchmetrics calculated by the branch metric calculator 310 to the previousstate path metric, the path metrics at the respective states are updatedby finding the minimum path metric among the calculated path metrics,and the survival path having the minimum path metric is selected. Infurther detail, the normalizing factor generator 329 generates thenormalizing factor (norm) for preventing the respective path metricsfrom being overflowed in step S321. The normalizing factor may bedefined by the minimum value among the path metrics at the respectivestates. The normalizing units 321 and 323 normalize the previous statepath metric in step S322 by the normalizing factor (norm) generated bythe normalizing factor generator 329. At this time, the normalizingunits 321 and 323 may normalize the previous state path metric bysubtracting the normalizing factor (norm) from the previous state pathmetric. In addition, the path metric adder 322 and 324 generate themetrics of the path to the current state from the respective branches instep S323 by adding the branch metrics of the branches, i.e., thebranches from the previous state to the current state, to the previousstate path metrics. Then, the path metric comparator 325 compares themetrics of paths to the current state for the respective branches, thevalues generated by the path metric adders 322 and 324, and selects thesurvival path in step S324. In addition, the path metric selector 325stores the path metric corresponding to the selected survival path inthe path metric storage unit 328.

Then, the path metric clipper 327 clips the path metric so that the pathmetric selected by the path metric selector 325 may not be overflowed,and outputs the clipped path metric.

The trace back unit 330 traces back the trellis of the transmitterconvolutional encoder based on the survival path from the ACS operator320, and generates the expanded decoded data in step S330.

In addition, the central bit sequence selector 400 selects the centralbit sequence of the expanded decoded data generated by the trace backunit 330, and outputs the selected central bit sequence in step S400.

The rearrange unit 500 rearranges an order of the central bit sequence,and generates the final decoded data in step S500.

The above described methods and apparatuses are not only realized by theexemplary embodiment of the present invention, but, on the contrary, areintended to be realized by a program for realizing functionscorresponding to the configuration of the exemplary embodiment of thepresent invention or a recoding medium recoding the program.

While this invention has been described in connection with what ispresently considered to be practical exemplary embodiments, it is to beunderstood that the invention is not limited to the disclosedembodiments, but, on the contrary, is intended to cover variousmodifications and equivalent arrangements included within the spirit andscope of the appended claims.

1. A Viterbi decoder comprising: a receiving buffer for receiving anencoding bit sequence in a convolutional encoding method from a channel;a received bit sequence expanding unit for receiving the encoding bitsequence corresponding to an encoding unit from the receiving buffer,and generating an expanded encoding bit sequence by expanding theencoding bit sequence more than twice, wherein some of an initial bitsequence or a last bit sequence of the expanded encoding bit sequencemay be omitted; a Viterbi decoding unit for receiving the expandedencoding bit sequence, Viterbi decoding the expanded bit sequence, andoutputting decoded data; a central bit sequence selector for selecting acentral bit sequence of the decoded data, and outputting the central bitsequence; and a rearrange unit for rearranging an order of the centralbit sequence, and generating final decoded data.
 2. The Viterbi decoderof claim 1, wherein the Viterbi decoding unit comprises: a branch metriccalculator for calculating branch metrics of branches by differencesbetween the expanded encoding bit sequence and encoding bits on atrellis of a transmitter convolutional encoder; an ACS operator foradding the branch metrics to previous state path metrics, calculatingmetrics of paths from the respective branches to a current state, andselecting a survival path for a path having a minimum path metric; and atrace back unit for tracing back the survival path, and outputtingdecoded data.
 3. The Viterbi decoder of claim 2, wherein the ACSoperation comprises: a path metric adder for adding the previous statepath metrics to branch metrics of branches from the previous state tothe current state, and generating the metrics of paths from therespective branches to the current state; a path metric comparator forcomparing the metrics of paths generated by the path metric adder, andselecting the survival path having the minimum path metric; a pathmetric selector for selecting a path metric corresponding to thesurvival path and outputting the selected path metric; and a path metricstorage unit for storing the selected path metric.
 4. The Viterbidecoder of claim 3, wherein the ACS operation comprises: a normalizingfactor generator generating a normalizing factor for preventing the pathmetric, the path metric accumulated as the trellis proceeds, from beingoverflowed; and a normalizing unit normalizing the previous state pathmetric by the normalizing factor generated by the normalizing factorgenerator.
 5. The Viterbi decoder of claim 4, wherein the normalizingfactor generator generates the normalizing factor which is the minimumpath metric among the previous state path metrics, and the normalizingunit subtracts the normalizing factor from the previous state value. 6.The Viterbi decoder of claim 3, further comprising a clipper forclipping the path metric when the path metric selected by the pathmetric selector is greater than a storing unit of the path metricstorage unit.
 7. The Viterbi decoder of claim 2, wherein the branchmetric calculator comprises: a distance calculator for calculating adistance value between the encoding bit sequence from the received bitsequence expanding unit and representative values of 0 and 1; and abranch metric adder for generating the branch metrics generated in astate transition by the distance value calculated by the distancecalculator.
 8. The Viterbi decoder of claim 7, further comprising abranch metric storage unit for storing the branch metrics generated bythe branch metric adder.
 9. A decoding method comprising: a) receivingan encoding bit sequence in a convolutional encoding method from achannel; b) generating an expanded encoding bit sequence for an encodingunit based on the encoding bit sequence, wherein the expanded encodingbit sequence is generated by expanding the encoding bit sequence morethan twice, and some of an initial bit sequence or a last bit sequenceof the expanded encoding bit sequence may be omitted; c) Viterbidecoding the expanded encoding bit sequence and outputting decoded data;d) selecting a central bit sequence of the decoded data; and e)rearranging an order of the central bit sequence and generating finaldecoded data.
 10. The decoding method of claim 9, wherein step ccomprises: calculating branch metrics of branches by differences betweenthe expanded encoding bit sequence and encoding bits on a trellis of atransmitter convolutional encoder; adding the branch metrics to previousstate path metric, calculating metrics of paths to a current state, andselecting a survival path for a branch having a minimum path metric; andtracing back the selected survival path, and outputting decoded data.11. The decoding method of claim 10, wherein the selecting of thesurvival path comprises: adding the previous state path metric to branchmetrics of branches from the previous state to the current state, andgenerating the metrics of paths from the respective branches to thecurrent state; comparing the generated path metrics, and selecting thesurvival path having the minimum path metric; selecting a path metriccorresponding to the survival path; and storing the selected pathmetric.
 12. The decoding method of claim 11, wherein the selecting ofthe survival path further comprises: generating a normalizing factorwhich is a minimum path metric among the previous state path metrics;and subtracting the normalizing factor from the previous state pathmetric.
 13. The decoding method of claim 11, wherein the selecting ofthe survival path further comprises clipping the selected path metric.14. The decoding method of claim 10, wherein the calculating of thebranch metric comprises: calculating a distance value between theencoding bit sequence and representative values of 0 and 1; andgenerating the branch metrics generated in a state transition by thedistance value.